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1999 data sheet m pd3799 mos integrated circuit the m pd3799 is a color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the m pd3799 has 3 rows of 5300 pixels, and each row has a single-sided readout type of charge transfer register. and it has reset feed-through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. therefore, it is suitable for 600 dpi/a4 color image scanners, color facsimiles and so on. features ? valid photocell : 5300 pixels 3 ? photocell's pitch : 7 m m ? line spacing : 28 m m (4 lines) red line-green line, green line-blue line ? color filter : primary colors (red, green and blue), pigment filter (with light resistance 10 7 lx?hour) ? resolution : 24 dot/mm a4 (210 297 mm) size (shorter side) 600 dpi us letter (8.5 11) size (shorter side) ? drive clock level : cmos output under 5 v operation ? data rate : 4 mhz max. ? power supply : +12 v ? on-chip circuits : reset feed-through level clamp circuits clamp pulse generation circuit voltage amplifiers ordering information part number package m pd3799cy ccd linear image sensor 32-pin plastic dip (400 mil) document no. s14083ej1v0ds00 (1st edition) date published april 1999 n cp(k) printed in japan 5300 pixels 3 color ccd linear image sensor the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd3799 2 data sheet s14083ej1v0ds00 block diagram 31 32 1 30 2 11 25 24 23 22 10 9 8 3 d14 d64 d65 d66 s5299 s5300 s1 s2 photocell (blue) transfer gate ccd analog shift register d67 d14 d64 d65 d66 s5299 s5300 s1 s2 photocell (green) transfer gate ccd analog shift register d67 d14 d64 d65 d66 s5299 s5300 s1 s2 photocell (red) transfer gate ccd analog shift register d67 tg1 (blue) f tg2 (green) f tg3 (red) f rb f 2 f 1 f 2 f 1 f gnd gnd v od v out 3 (red) v out 2 (green) v out 1 (blue) clamp pulse generator
m pd3799 3 data sheet s14083ej1v0ds00 pin configuration (top view) ccd linear image sensor 32-pin plastic dip (400 mil) ? m pd3799cy caution leave pins 6, 7, 12, 13, 20, 21, 26, 27 (ic) unconnected. 1 2 3 4 5 6 7 8 9 10 11 31 30 29 28 27 26 25 24 23 22 32 nc nc v out 2 v out 1 ic 1 f tg1 f no connection no connection output signal 2 (green) output signal 1 (blue) output drain voltage internal connection shift register clock 1 transfer gate clock 2 (for green) v out 3 gnd ic ic 1 f tg3 f no connection no connection output signal 3 (red) ground reset gate clock shift register clock 2 internal connection internal connection shift register clock 1 5300 5300 5300 red green blue 1 1 1 internal connection transfer gate clock 1 (for blue) transfer gate clock 3 (for red) v od ic 2 f 2 f shift register clock 2 gnd ground rb f nc nc tg2 f 12 13 14 15 16 21 20 19 18 17 ic internal connection ic internal connection nc no connection nc no connection nc no connection ic internal connection ic internal connection nc no connection nc no connection nc no connection
m pd3799 4 data sheet s14083ej1v0ds00 photocell structure diagram photocell array structure diagram (line spacing) m 7 m m 4 m m m 3 channel stopper aluminum shield blue photocell array 7 m m green photocell array 7 m m red photocell array 7 m m 4 lines (28 m) m 4 lines (28 m) m
m pd3799 5 data sheet s14083ej1v0ds00 absolute maximum ratings (t a = +25 c) parameter symbol ratings unit output drain voltage v od C0.3 to +15 v shift register clock voltage v f 1 , v f 2 C0.3 to +8 v reset gate clock voltage v f rb C0.3 to +8 v transfer gate clock voltage v f tg1 to v f tg3 C0.3 to +8 v operating ambient temperature t a C25 to +60 c storage temperature t stg C40 to +70 c caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. recommended operating conditions (t a = +25 c) parameter symbol min. typ. max. unit output drain voltage v od 11.4 12.0 12.6 v shift register clock high level v f 1h , v f 2h 4.5 5.0 5.5 v shift register clock low level v f 1l , v f 2l C0.3 0 +0.5 v reset gate clock high level v f rbh 4.5 5.0 5.5 v reset gate clock low level v f rbl C0.3 0 +0.5 v transfer gate clock high level v f tg1h to v f tg3h 4.5 v f 1h note v f 1h note v transfer gate clock low level v f tg1l to v f tg3l C0.3 0 +0.5 v data rate f f rb C 1.0 4.0 mhz note when transfer gate clock high level (v f tg1h to v f tg3h ) is higher than shift register clock high level (v f 1h ), image lag can increase.
m pd3799 6 data sheet s14083ej1v0ds00 electrical characteristics t a = +25 c, v od = 12 v, data rate (f f rb ) = 1 mhz, storage time = 5.5 ms, input signal clock = 5 v p-p light source: 3200 k halogen lamp +c-500s (infrared cut filter, t = 1mm) + ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 2.0 2.5 C v saturation exposure red ser 0.223 lx?s green seg 0.245 lx?s blue seb 0.409 lx?s photo response non-uniformity prnu v out = 1.0 v 6 20 % average dark signal ads light shielding 0.2 2.0 mv dark signal non-uniformity dsnu light shielding 1.5 3.0 mv power consumption p w 360 540 mw output impedance z o 0.5 1 k w response red r r 7.8 11.2 14.6 v/lx?s green r g 7.1 10.2 13.3 v/lx?s blue r b 4.2 6.1 8.0 v/lx?s image lag il v out = 1.0 v 1.5 7.0 % offset level note1 v os 4.0 5.5 7.0 v output fall delay time note2 t d v out = 1.0 v 50 ns total transfer efficiency tte v out = 1.0 v, 92 98 % data rate = 4 mhz response peak red 630 nm green 540 nm blue 460 nm dynamic range dr1 v sat /dsnu 1666 times dr2 v sat / s 2500 times reset feed-through noise note1 rftn light shielding C1000 C300 +500 mv random noise s light shielding C 1.0 C mv notes 1. refer to timing chart 2 . 2. when the fall time of f 1 (t1) is the typ. value (refer to timing chart 2 ).
m pd3799 7 data sheet s14083ej1v0ds00 input pin capacitance (t a = +25 c, v od = 12 v) parameter symbol pin name pin no. min. typ. max. unit shift register clock pin capacitance 1 c f 1 f 1 9 400 pf 24 400 pf shift register clock pin capacitance 2 c f 2 f 2 8 400 pf 25 400 pf reset gate clock pin capacitance c f rb f rb 3 15 pf transfer gate clock pin capacitance c f tg f tg1 23 100 pf f tg2 22 100 pf f tg3 10 100 pf remark pins 9 and 24 ( f 1), 8 and 25 ( f 2) are each connected inside of the device.
m pd3799 8 data sheet s14083ej1v0ds00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 61 62 63 64 65 66 5363 5364 5365 5366 5367 5368 5369 optical black (49 pixels) invalid photocell (2 pixels) valid photocell (5300 pixels) invalid photocell (3 pixels) f tg1 to tg3 f 1 2 f f rb f v out 1 to v out 3 note f rb pulse continuously during this period, too. note input the note timing chart 1 (for each color)
m pd3799 9 data sheet s14083ej1v0ds00 v out f rb f 2 f 1 90 % 10 % 90 % 10 % 90 % 10 % + _ rftn rftn v os t2 t1 t4 t6 t3 t5 t d timing chart 2 (for each color) 10 %
m pd3799 10 data sheet s14083ej1v0ds00 f tg1 to f tg3, f 1, f 2 timing chart symbol min. typ. max. unit t1, t2 0 25 C ns t3 20 50 C ns t4 110 250 C ns t5, t6 0 25 C ns t7, t8 0 50 C ns t9 3000 10000 C ns t10, t11 900 1000 C ns f 1, f 2 cross points remark adjust cross points of f 1 and f 2 with input resistance of each pin. 1 f 2 f t10 90 % 10 % 90 % tg1 to tg3 f t7 t9 t8 t11 f 2 f 1 f 2.0 v or more 0.5 v or more
m pd3799 11 data sheet s14083ej1v0ds00 d j : dark signal of valid pixel number j dsnu (mv) : maximum of ? d j - ads ? j = 1 to 5300 prnu (%) = x = x j : output voltage of valid pixel number j d x d x : maximum of ? x j - x ? x 5300 s j=1 5300 x j 100 ads (mv) = d j : dark signal of valid pixel number j 5300 s j=1 5300 d j definitions of characteristic items 1. saturation voltage: v sat output signal voltage at which the response linearity is lost. 2. saturation exposure: se product of intensity of illumination (i x ) and storage time (s) when saturation of output voltage occurs. 3. photo response non-uniformity: prnu the output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. this is calculated by the following formula. 4. average dark signal: ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula. 5. dark signal non-uniformity: dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula. x register dark dc level v out d x ads dsnu register dark dc level v out
m pd3799 12 data sheet s14083ej1v0ds00 6. output impedance: z o impedance of the output pins viewed from outside. 7. response: r output voltage divided by exposure (ix?s). note that the response varies with a light source (spectral characteristic). 8. image lag: il the rate between the last output voltage and the next one after read out the data of a line. 9. random noise: s random noise s is defined as the standard deviation of a valid pixel output signal with 100 times (=100 lines) data sampling at dark (light shielding). v i : a valid pixel output signal among all of the valid pixels for each color this is measured by the dc level sampling of only the signal level, not by cds (correlated double sampling). v out f tg light v out on off v 1 v 1 il (%) = 100 v out v 1 v 100 v 2 ? ? line 2 line 100 line 1 v out s (mv) = , v = s i=1 100 (v i ?v) 2 s i=1 100 v i 100 100 1
m pd3799 13 data sheet s14083ej1v0ds00 standard characteristic curves (nominal) dark output temperature characteristic storage time output voltage characteristic (t a = +25 ?) operatin g ambient temperature t a (?) stora g e time (ms) 8 4 2 1 0.5 0.25 0.1 10 0 20304050 relative output voltage relative output voltage 2 1 0.2 0.1 1510 400 500 600 700 800 100 80 60 40 20 0 b b g r g response ratio (%) wavelength (nm) total spectral response characteristics (without infrared cut filter and heat absorbing filter) (t a = +25 c)
m pd3799 14 data sheet s14083ej1v0ds00 application circuit example caution leave pins 6, 7, 12, 13, 20, 21, 26, 27 (ic) unconnected. remark the inverters shown in the above application circuit example are the 74hc04. v out 3 pd3799 m v out 1 gnd ic ic nc ic gnd ic f 2 f 2 f tg3 f 1 f tg1 f 1 f tg2 47 w 4.7 w 4.7 w 4.7 w 4.7 w 4.7 w 4.7 w 4.7 w 132 31 30 29 28 27 26 25 24 23 22 2 3 4 5 6 7 8 9 10 11 b3 v out 2 v od nc f rb nc nc b2 +12 v 10 w m 0.1 f m 47 f/25 v m 0.1 f m 10 f/16 v tg 1 f f rb f 2 f + b1 +5 v +5 v + m 0.1 f m 10 f/16 v + ic ic ic ic 21 20 12 13 nc nc nc nc 19 18 14 15 nc nc 17 16
m pd3799 15 data sheet s14083ej1v0ds00 47 f/25 v b1 to b3 equivalent circuit + m 12 v 100 w 100 w ccd v out 2sc945 2 k w
m pd3799 16 data sheet s14083ej1v0ds00 package drawing ccd linear image sensor 32-pin plastic dip (400 mil) outline drawings (unit : mm) 4.0 0.3 1 2.58 0.3 0.25 0.05 10.16 (1.80) 2 3 0~10 1st valid pixel 4 name dimensions refractive index plastic cap 52.2 6.4 0.7 1.5 the 1st valid pixel the surface of the chip the bottom of the package 1 2 3 the center of the pin1 the top of the cap the surface of the chip 32c-1ccd-pkg1-1 thickness of plastic cap over ccd chip 4 (5.42) 9.05 0.3 9.25 0.3 12.6 0.5 54.8 0.5 55.2 0.5 1.02 0.15 0.46 0.06 4.21 0.5 4.55 0.5 4.1 0.5 38.1 2.54
m pd3799 17 data sheet s14083ej1v0ds00 recommended soldering conditions when soldering this product, it is highly recommended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. for more details, refer to our document "semiconductor device mounting technology manual"(c10535e) . type of through-hole device m pd3799cy : ccd linear image sensor 32-pin plastic dip (400 mil) caution during assembly care should be taken to prevent solder or flux from contacting the plastic cap. the optical characteristics could be degraded by such contact. conditions pin temperature: 300 c or below, heat time: 3 seconds or less (per pin) process partial heating method
m pd3799 18 data sheet s14083ej1v0ds00 notes on cleaning the plastic cap 1 cleaning the plastic cap care should be taken when cleaning the surface to prevent scratches. the optical characteristics of the ccd will be degraded if the cap is scratched during cleaning. we recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. excessive pressure should not be applied to the cap during cleaning. if the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 recommended solvents the following are the recommended solvents for cleaning the ccd plastic cap. use of solvents other than these could result in optical or physical degradation in the plastic cap. please consult your sales office when considering an alternative solvent. solvents symbol ethyl alcohol etoh methyl alcohol meoh isopropyl alcohol ipa n-methyl pyrrolidone nmp
m pd3799 19 data sheet s14083ej1v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd3799 [memo] the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8

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